**The misunderstanding**

The basic model of an NCL system is NCL combinational circuits between delay insensitive registers managed by a handshake protocol.

**The understanding**

Null Convention Logic fully integrates function, memory and flow control. This integration is best understood and most effectively used in terms of oscillations linked by shared completeness behaviors.

With NCL the combinational function, the flow registration and the flow control can all be integrated into very efficient structures of spontaneously flowing oscillations linked by shared completeness behaviors. Viewing these three elements as inherently different just limits understanding the integrated efficiencies that NCL can inherently deliver.

**Simple example**

We illustrate this with a simple combinational circuit shown below that adds a binary variable to a trinary variable and produces a quaternary variable.

the circuit is characterized with the equation set:

quaternary/0 = binary/0 & trinary/0;

quaternary/1 = trinary/0 & binary/1 | trinary/1 & binary/0;

quaternary/2 = trinary/2 & binary/0 | trinary/1 & binary/1;

quaternary/3 = binary/1 & trinary/2;

To this circuit we add flow registration by &ing each equation with quaternaryclose and adding completeness to the quaternary path. The quaternaryclose enable rank is integral to the data path. The completeness is not part of the data path and is outside the equation set.

quaternary/0 = quaternaryclose & binary/0 & trinary/0;

quaternary/1 = quaternaryclose & (trinary/0 & binary/1 | trinary/1 & binary/0);

quaternary/2 = quaternaryclose & (trinary/2 & binary/0 | trinary/1 & binary/1);

quaternary/3 = quaternaryclose & binary/1 & trinary/2;

The added logic performs flow registration for the data path.

A data wavefront arrives from upstream. If downstreamclose is null the data wavefront will be maintained by upstream. When downstreamclose becomes data the data wavefront is allowed through the enable rank whereupon the completeness detects the data wavefront and indicates with upstreamcomp that the data wavefront has been received, is being maintained and that a null wavefront can be sent. The data wavefront will be maintained by the enable rank as long as downstreamclose remains data.

Downstreamclose becomes null when a similar structure downstream, passes and maintains the data wavefront, its completeness is detected and downstreamcomp becomes data which sets downstreamclose to null.

The requested null wavefront arrives from upstream. If downstreamclose is data the null wavefront will be maintained by upstream. When downstreamclose becomes null the null wavefront is allowed through the enable rank whereupon the completeness detects the null and indicates with upstreamcomp that the null wavefront has been received, is being maintained and that a data wavefront can be sent. The null wavefront will be maintained by the enable rank as long as downstreamclose remains null.

Downstreamclose becomes data when a similar structure downstream, passes and maintains the null wavefront, its completeness is detected and downstreamcompbecomes null which sets downstreamclose to data.

and so on….

The movie below with auto produce on each input and auto consume on the output illustrates the behavior of the three linked oscillations.

The added structure is providing flow control and memory and can legitimately be called a register. So the blue circled circuit above can be characterized as a combinational circuit playing into a register. The blue circled circuit can also be characterized as a shared completeness behavior linking three oscillations.

But the added structure is not some special kind of extra-logical memory circuit. It is just an NCL circuit and it can be optimized with another NCL circuit. This optimization can be performed in terms of the equation set. For instance, we can distribute quaternaryclose over the terms and the following equation set results

quaternary/0 = quaternaryclose & binary/0 & trinary/0;

quaternary/1 = quaternaryclose & trinary/0 & binary/1 | quaternaryclose & trinary/1 & binary/0;

quaternary/2 = quaternaryclose & trinary/2 & binary/0 | quaternaryclose & trinary/1 & binary/1;

quaternary/3 = quaternaryclose & binary/1 & trinary/2;

which maps directly to the following circuit.

The registration and memory is integrated into the combinational circuit. There is no identifiable structure that can be characterized as a separate register. The blue circled circuit can still be characterized as a shared completeness behavior linking three oscillations, but not as a combination circuit playing into a register.

The equations can also be optimized by factoring (see LDD chapter4)

quaternary/0 = quaternaryclose & binary/0 & trinary/0;

quaternary/1 = quaternaryclose & (trinary/0 & binary/1 | trinary/1 & binary/0);

quaternary/2 = quaternaryclose & (trinary/2 & binary/0 | trinary/1 & binary/1);

quaternary/3 = quaternaryclose & binary/1 & trinary/2;

which can be mapped directly into the following circuit.

Again the flow control is fully integrated into the combinational expression. The blue circled circuit can be characterized as a shared completeness behavior linking three oscillations. Again, there is no element that can be identified as a registration behavior separate from the combinational function behavior.

Any circuit realization of the equation set can be characterized as a shared completeness behavior linking three oscillators. But only one realization can be characterized as having an identifiable register. With NCL, the characterization of oscillations linked by shared completeness behaviors is the more fertile conceptual and linguistic view. Viewing NCL in terms of of combinational circuits between registers with handshake control limits understanding the range of expressivity of NCL and limits appreciating its inherent efficiencies.