Null Convention Logic

Note on Browsers

Null Convention Logic is a complete and coherent logic sufficiently expressive to implement entire systems solely in terms of NCL. Extra logical elements such as a time referent, timing analysis and DQ flip flops are not needed. NCL engenders a model of computation quite different from the Clocked Boolean Logic (CBL) model of computation leading to some confusion. Our goal here is to address these confusions, to clarify the NCL model of computation and to highlight its practical advantages.

In these discussions a level of familiarity with NCL is assumed. The first order reference for NCL referred to as LDD is:

Karl M. Fant, Logically Determined Design: Clockess System Design with NULL Convention Logic, (Hoboken, New Jersey, Wiley Interscience, 2005).

A note on terminology.

Why NCL™ can be low power
The first impression of many people is that NCL must necessarily be slower, bigger and require more power because it is dual-rail and has a null propagation cycle. So,how can it be that  8 and 16 bit NCL processors have been demonstrated to achieve 1/3 the power consumption of functionally equivalent CBL processors with comparable throughput and with only 1.3 the area. Steering and multi-rail representation deliver part of the advantage. Registration and flow control can be efficiently integrated with NCL in ways that cannot be achieved with CBL.

Why NCL can be fast
NCL clockless circuit design delivers average case throughput performance in contrast to the synchronous clock tic behavior delivered by CBL.  This lack of guaranteed latency is a discomfort for some but average case throughput can be much greater than synchronous throughput.  The myth of latency

How is NCL different?
NCL engenders a model of computation that behaves solely in terms of logical relationships, does not relate to a clock and consequently happens to behave asynchronously. So how is NCL different from design methods whose only goal is asynchronous behavior.

NCL Background

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