The NCL sandbox on GitHub is a collection of Verilog designs implementing NCL circuits starting with the simplest circuits and progressing in functionality and complexity. The Verilog designs are coded in Iverilog and the waveforms can be viewed with GTKWave. Both of which are freely available. The NCL library of threshold functions is implemented as Verilog sequential UDPs and the Verilog programs are in terms of references to the library. Download directory of NCL graphic symbols.
The composition of several counter circuits is presented all derived from a symbolic specification which is verified solely in terms of its logical relations. The counters are compared in a spreadsheet There is also a demonstration of the meaning of logically determined design.
Several 32 bit adder circuits are presented with different full adders and different compositions of the full adders. Statistic are collected and the adders compared in the spreadsheet. Finally composition is demonstrated with counters connected to an adder which adds the counts.
Steering the flow of data wavefronts through a background of null emptiness is presented. The steering logic structures are introduced, the OR related flow paths resulting from the steering are introduced, the potential races from free flowing OR related paths is demonstrated and how to manage the flows to avoid the races. Finally, a prototype multi-function ALU component is presented. Some basic numbers are collected in the spreadsheet.
An 8 bit 2D pipelined, high throughput array multiplier is presented as the first multiplier posted as the native NCL multiplier design. Later, other designs that mimic more common designs will be added.
The use of arbiters to manage independently flowing paths into coordinated multi-rail variables is presented. Examples are two independent rails to dual rail, three independent to rails to a trinary variable, four independent rails to a quaternary variable and two independent dual rail variables into a single dual rail variable.
A new library NCL_LIB_unity.v is introduced and demonstrated in which the delay of all functions is 1 ps. It is useful for a first order check of logical determination.
Shifter circuits are presented. The shift operation is unique because it does not lend itself to 2D pipelining. Three different shift structures are presented and two examples of the interaction of different wavefront flows: 2D pipelining flow, ragged flow and full word completeness flow.
Pipeline rings are one of the more mysterious aspects of logically determined behavior. This sandbox discusses how to analyze the behaviors of a ring. It covers wavefronts and bubbles and wavefront limited, bubble limited and delay limited behavior. A set of illustrative movies can be downloaded as well as a spreadsheet for analyzing ring behavior.